Education, Science, Technology, Innovation and Life
Open Access
Sign In

Research on the Design and Optimization of Low-Power Operational Amplifiers Based on CMOS Technology

Download as PDF

DOI: 10.23977/jeis.2026.110109 | Downloads: 0 | Views: 20

Author(s)

Haiyang Yang 1

Affiliation(s)

1 Minzu University of China, Beijing, 100081, China

Corresponding Author

Haiyang Yang

ABSTRACT

With the rapid advancement of Internet of Things (IoT), wearable electronics, and implantable medical devices, integrated circuits are facing unprecedentedly stringent power constraints. As a core building block of analog front-end circuits, the power efficiency of the operational amplifier (Op-Amp) directly dictates the overall energy efficiency of the system. This paper focuses on the design of low-power operational amplifiers based on mainstream CMOS technology and proposes a novel co-optimization paradigm that synergistically integrates subthreshold biasing, dynamic biasing, and gain-boosting techniques. This paradigm is aimed at systematically overcoming the inherent trade-off among gain, bandwidth, and power consumption that plagues conventional low-power designs. The study first provides an in-depth analysis of the operating mechanism of MOS transistors in the subthreshold region and its potential for extreme compression of the op-amp's static power dissipation. Subsequently, an innovative dynamic biasing circuit, adaptively controlled by the input signal amplitude, is introduced. This circuit enables the op-amp to maintain ultra-low static power during small-signal operation while automatically injecting auxiliary bias current during large-signal transients to enhance the slew rate (SR) and unity-gain bandwidth (UGBW), thereby effectively balancing static and dynamic performance. Furthermore, a local gain-boosting technique is employed to significantly increase the DC open-loop gain without substantially raising power consumption, meeting the demands of high-precision applications. Finally, the proposed architecture is implemented and verified through simulation using a 65-nm CMOS process. Results demonstrate that the designed op-amp achieves a 98-dB open-loop gain, a 1.5-MHz unity-gain bandwidth, and a 0.8-V/μs slew rate, all while consuming only 1.2 μW of static power. Its figure-of-merit (FOM) exhibits an approximately 35% improvement over state-of-the-art counterparts. This work provides a practical and theoretically sound pathway for the design of next-generation ultra-low-power, high-performance analog integrated circuits.

KEYWORDS

Low power; Operational amplifier; CMOS technology; Subthreshold biasing; Dynamic biasing; Gain boosting

CITE THIS PAPER

Haiyang Yang. Research on the Design and Optimization of Low-Power Operational Amplifiers Based on CMOS Technology. Journal of Electronics and Information Science (2026). Vol. 11, No. 1, 67-74. DOI: http://dx.doi.org/10.23977/10.23977/jeis.2026.110109.

REFERENCES

[1] Razavi B. Design of Low-Voltage, Low-Power CMOS Operational Amplifiers[J]. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1994, 41(12): 848-858. DOI: 10.1109/81.340841.
[2] Silva-Martinez J, Steyaert M S J, Sanchez-Sinencio E.Loop gain characteristics of buffer amplifiers[J].IEEE Journal of Solid-State Circuits, 2002, 37(6): 707-715. DOI: 10.1109/JSSC.2002.1002661.
[3] Giannini V, Nuzzo P, Van der Plas G, et al.A 1.2 mW 130 MHz 70 dB dynamic range low-distortion variable gain amplifier in 90 nm digital CMOS[J].IEEE Journal of Solid-State Circuits, 2008, 43(1): 135-148. DOI: 10.1109/JSSC.2007.911618.
[4] Chandrakasan A P, Sheng S, Brodersen R W. Low-power CMOS digital design[J]. IEEE Journal of Solid-State Circuits, 1992, 27(4): 473-484. DOI: 10.1109/4.124126.

Downloads: 17185
Visits: 779663

Sponsors, Associates, and Links


All published work is licensed under a Creative Commons Attribution 4.0 International License.

Copyright © 2016 - 2031 Clausius Scientific Press Inc. All Rights Reserved.