FPGA Implementation of LDPC Decoder with Low Complexity
DOI: 10.23977/jeeem.2017.11003 | Downloads: 35 | Views: 4359
Zheng Hao 1, Li Lintao 2
1 Schoold of Information and Electronics, Beijing Institute of Technology, Beijing; 100081, China
2 School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing; 100876, China
Corresponding AuthorLi Lintao
According to the limitation of resources on satellite, this paper focuses on the design and realization of low complexity LDPC decoder. A new implementation method of LDPC decoder is proposed, a various kinds of LDPC codes could be supported. Finally, a (4096, 2048) LDPC decoder is implemented for verification based on a Xilinx Vertex4 xc4vsx35 FPGA platform. The implementation result shows that only 4% FPGA logic resources were consumed and the maximum clock frequency could achieve 180MHz.
KEYWORDSLDPC, Decoder, Low Complexity
CITE THIS PAPER
Lintao, L. , Hao Z. (2017) FPGA Implementation of LDPC Decoder with Low Complexity. Journal of Electrotechnology, Electrical Engineering and Management (2017) 1: 12-17.
 Gallager R G. Low-density parity-check codes[J]. IRE Transactions on Information Theory, 1962, 8(1): 21-28.
 Verdier F, Declercq D. A Low-Cost Parallel Scalable FPGA Architecture for Regular and Irregular LDPC Decoding[J]. IEEE Transactions on Communications, 2006, 54(7): 1215-1223.
 Arnone L J, Castineira Moreira J, Farrell P G. Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders[J]. Communications, 2012, 6(12): 1670-1675.
 Wang B, Wan L. FPGA Implement for High Performance and Low Complex LDPC Decoder[J]. Modern Electronics Technique, 2008(18): 135-138. (in Chinese)
 Zhu J, Zhang H B, Pan Y. A Low-complexity Iterative Decoding Algorithm for LDPC Codes[J]. Telecommunication Engineering, 2006(5): 95-97. (in Chinese)
 Yin S S, Wang Z X. Low complexity encoding and decoding research of DVB-S2 LDPC[J]. Journal of Chongqing University of Posts & Telecommunications, 2012, 24(4): 457-461.
 Xiaoheng Chen, Qin Huang, Shu Lin, Akella V. FPGA-Based Low-Complexity High-Throughput Tri-Mode Decoder for Quasi-Cyclic LDPC Codes [C]. Communication, Control and Computing, Monticello: IEEE, 2009: 600-606.
 Daesun Oh, Parhi K K. Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes [C]. Signal Processing Systems Design and Implementation, Banff, Alta: IEEE, 2006: 262-267.
 Chen J H, Fossorier M P C. Density evolution for two improved BP-based decoding algorithms of LDPC codes[J]. IEEE Communications Letters, 2002, 6(5): 208-210.
 Y. Kou, S. Lin, and M.P.C. Fossorier. Low-density parity-check codes based on finite geometries: a rediscovery and new results. IEEE Trans. Inform. Theory, 47(7):2711–2736, Nov. 2001.
 J. Kang, Construction, Decoding and Application of Low-density Parity-check Codes. University of California, Davis, 2009.