Author(s)

Yuemu Fei ¹

Affiliation(s)

¹ Sunmmio Technology (Beijing) Co., Ltd., Beijing, 100080, China

Corresponding Author

Yuemu Fei

ABSTRACT

The rapid adoption of heterogeneous multicluster architectures in modern Systems-on-Chip (SoCs) has increased the need for scalable and accurate simulation tools. GEM5 continues to be widely used across academia and industry for microarchitectural exploration, yet its single-threaded event loop limits simulation throughput when evaluating SoCs composed of many interacting CPU clusters, GPUs, NPUs, and memory subsystems. To overcome this bottleneck, we propose PGSI (Parallel GEM5-based Simulation Infrastructure), a parallel simulation framework designed to extend GEM5 while preserving cycle-accurate fidelity. PGSI introduces cluster-level parallelism, a deterministic global synchronization barrier, a lock-free shared-memory emulation layer, and a cycle-accurate Network-on-Chip (NoC) timing model. Across PARSEC, SPEC CPU2017, MobileNet inference, and Android micro-services, PGSI achieves an average 3.4× speed-up over baseline GEM5 while maintaining <2% deviation in IPC, memory latency, and end-to-end execution time. PGSI demonstrates that cycle-accurate simulation of large heterogeneous SoCs can be parallelized effectively without rollback or hardware-assisted execution, providing a practical foundation for future architectural research.

KEYWORDS

Parallel Simulation; Cycle-Accurate Modeling; Heterogeneous Multicluster SoC; Network-on-Chip (NoC); Shared-Memory Emulation

CITE THIS PAPER

Yuemu Fei, A Parallel GEM5-Based Simulation Infrastructure for Multicluster SoC Performance Evaluation. Journal of Network Computing and Applications (2025) Vol. 10: 113-120. DOI: http://dx.doi.org/10.23977/jnca.2025.100113.

REFERENCES

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